The integration of hundreds of millions of circuit elements, such as transistors, on a single integrated circuit necessitates further dramatic scaling down or micro-miniaturization of the physical dimensions of circuit elements, including interconnection structures. Micro-miniaturization has engendered a dramatic increase in transistor engineering complexity, such as the inclusion of lightly doped drain structures, multiple implants for source/drain regions, silicidation of gates and source/drains, and multiple sidewall spacers, for example.
The drive for high performance requires high speed operation of microelectronic components requiring high drive currents in addition to low leakage, i.e., low off-state current, to reduce power consumption. Typically, the structural and doping parameters tending to provide a desired increase in drive current adversely impact leakage current.
Metal gate electrodes have evolved for improving the drive current by reducing polysilicon depletion. However, simply replacing polysilicon gate electrodes with metal gate electrodes may engender issues in forming the metal gate electrode prior to high temperature annealing to activate the source/drain implants, as at a temperature in excess of 900° C. Such fabrication techniques may degrade the metal gate electrode or cause interaction with the gate dielectric, thereby adversely impacting transistor performance.
Replacement gate techniques have been developed to address problems attendant upon substituting metal gate electrodes for polysilicon gate electrodes. For example, a polysilicon gate is used during initial processing until high temperature annealing to activate source/drain implants has been implemented. Subsequently, the polysilicon is removed and replaced with a metal gate.
Additional issues arise with lateral scaling, such as the formation of contacts. For example, once the contacted gate pitch gets to about 64 nanometers (nm), there is not enough room to land a contact between the gate lines and still maintain reliable electrical isolation properties between the gate line and the contact. Self-aligned contact (SAC) methodology has been developed to address this problem. Conventional SAC approaches involve recessing the replacement metal gate structure, which includes both work function metal liners (e.g. TiN, TaN, TaC, TiC, TiAlN, etc.) and conducting metal (e.g., W, Al, etc.), followed by a dielectric cap material deposition and chemical mechanical planarization (CMP). However, to set the correct workfunction for the device, sometimes thick work function metal liners are required (e.g., a combination of different metals such as TiN, TiC, TaC, TiC, or TiAlN with a total thickness of more than 7 nm). As gate length continues to scale down, for example for sub-15 nm gates, the replacement gate structure is so narrow that it will be “pinched-off” by the work function metal liners alone, with little or no space remaining for the lower resistance gate metal. This will cause high resistance issue for devices with small gate lengths, and will also cause problems in the SAC replacement gate metal recess, where the metal gate structures for long channel devices are significantly different from short channel devices.
A need therefore exists for a methodology enabling the fabrication of semiconductor devices including integrating both metal replacement gates and self-aligned contacts for both small gate length and larger gate length structures with thick work function metal liner compatibility. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings, the brief summary, and this background of the invention.